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SUMMARY:Technical Webinar – Dr. Matt Weimer\, Forge Nano
DESCRIPTION:Where: Online via Zoom \nWhen: Wednesday\, July 1\, from Noon to 1 p.m. (EDT) \nTopic: Enabling WBG and UWBG Devices with High-Deposition-Rate\, Efficient ALD \nPresenter: Dr. Matt Weimer\, Forge Nano \nBio \nDr. Matt Weimer is a surface chemist specializing in atomic layer deposition (ALD) for both wafer-scale and powder applications. He began his career at the Illinois Institute of Technology\, \ncompleting a PhD in Chemistry while holding a graduate appointment at Argonne National Laboratory (ANL). His doctoral work focused on synthesizing novel ALD precursors and pioneering the use of in situ X-ray absorption spectroscopy (XAS) to elucidate surface reaction mechanisms. \nFollowing a postdoctoral appointment at ANL in fundamental battery research\, Dr. Weimer joined Lam Research in New Products Development\, contributing to next-generation process technologies. For the past five years\, he has led the wafer development team at Forge Nano\, overseeing applications development\, customer demonstrations\, and the company’s wafer-scale ALD laboratories. He played a central role in launching TEPHRA\, Forge Nano’s ALD cluster platform uniquely designed for the More-than-Moore market. \n\nAbstract: This presentation details the modeling efforts conducted in Silvaco Victory Device at Texas Tech University on ultra-high voltage SiC SOS diodes\, demonstrating the viability of transition to wide-bandgap semiconductors for pulsed-power electronics applications. The transition to SiC SOS diodes is advantageous in pulsed power systems as it offers up to a 20x reduction in required devices compared to silicon\, thus increasing system reliability\, efficiency\, and power density. Featured in this presentation is the physical characterization and modeling of a SiC drift step recovery diode (DSRD)\, the design of the ultra-high voltage SiC SOS device\, several single-device testbed simulations\, and the successful simulation of a five-device series stack delivering a 100 kV\, 180 MW pulse. \nAbstract \nAtomic layer deposition (ALD) has repeatedly transformed microelectronics manufacturing\, from enabling high-k gate dielectrics in logic to making 3D NAND architectures possible\, by delivering high-quality\, conformal films where faster deposition techniques fall short. A similar inflection point is emerging in wide band gap (WBG) and ultra-wide band gap (UWBG) devices. ALD first entered these markets as a high-quality environmental barrier for GaN and GaAs\, but its advantages in thickness control\, conformality\, and dielectric performance are now driving broader adoption in GaN power/RF and SiC devices. As trench devices emerge and performance requirements heighten\, ALD is increasingly evaluated for roles such as high-quality dielectrics\, passivation layers\, and interface defect reduction. However\, concerns remain around whether ALD can meet high-volume manufacturing (HVM) throughput and cost targets. \n\nTo address these challenges\, Forge Nano has developed a high-efficiency\, single-wafer thermal ALD solution for 200 mm and smaller wafers\, integrated into a modern cluster platform designed for manufacturability and serviceability. Beyond established moisture-barrier applications in WBG devices\, we are advancing high-quality dielectric ALD films for GaN and SiC power electronics and extending this work to emerging UWBG materials such as diamond and Ga₂O₃. \nThis talk will highlight how the Forge Nano TEPHRA ALD cluster tool achieves higher deposition rates with significantly improved precursor utilization\, enabling cost-effective ALD for the WBG and UWBG markets. Data on moisture-barrier performance and dielectric properties on device-relevant substrates will be compared against incumbent solutions. Finally\, we will explore future device architectures and applications uniquely enabled by high-deposition rate and efficient ALD. \n\nZOOM WEBINAR LINK
URL:https://poweramericainstitute.org/event/technical-webinar-dr-matt-weimer-forge-nano/
CATEGORIES:Webinars
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