SemiX Webinar: SiC Fabrication in a Silicon Fab

The webinar is free and open to all

Who and What: PowerAmerica Executive Director and CTO Victor Veliadis will present a webinar titled “SiC Fabrication in a Silicon Fab” organized by SemiX, the Electron Devices Society Chapter of the IEEE Bombay Section and the Indian Institute of Technology (IIT) Bombay.

When: 8 to 9 a.m. EDT, Wednesday, July 17

Where: Online via Microsoft Teams – Link to Join (Meeting ID: 457 556 440 720; Passcode: rbYhDM)


SiC chips are displacing their incumbent silicon counterparts in several high-volume power
applications. As SiC market share continues to grow, the industry is lifting the remaining barriers
to mass commercialization including the higher-than-silicon chip cost that increases
disproportionately with area, defects that limit chip yield and area, reliability and ruggedness
concerns, and the need for a trained workforce to skillfully insert SiC devices into power
electronics circuits.

With respect to fabrication, the SiC industry is successfully leveraging the fully-depreciated
legacy silicon fab infrastructure, and is making the relatively small financial investments needed to
allow mature silicon fabs to process SiC. Consequently, SiC chip fabrication alongside silicon
has emerged as a cost-effective model that exploits silicon manufacturing economies of scale.
In this tutorial, key aspects of SiC fabrication technology will be summarized with an
emphasis on non-silicon-compatible processes streamlined for mass SiC manufacturing. The
latter include dry etching SiC, substrate thinning, heated implantation and high-temperature
annealing, CTE-matched metallization, ohmic contact formation, improved gate oxide
interface quality, transparent wafer handling, as well as edge termination techniques that
maximize blocking voltage.