Jack Knoll

School/year: Virginia Tech, Ph.D.
Graduate/Undergraduate: Graduate
Graduation Date: Spring 2025
Major: Electrical Engineering
Concentration: Power Electronics Packaging
PowerAmerica Project: PCB-embedded 1.2 kV SiC MOSFET half-bridge package for a 22 kW on-board charger; 1.2 kV SiC MOSFET full-bridge power module with integrated gate driver and coupled inductor; characterization of 4.5 kV charge-balanced SiC MOSFETs; a low thermal resistance package for a Ga2O3 Schottky diode; evaluation of methods to improve the case-to-board thermal resistances of surface mount SiC MOSFETs.
Areas of Expertise: Power semiconductor packaging design, fabrication, and testing; power semiconductor characterization; junction-to-case thermal resistance measurement